Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

E-16 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-15. #D - Denormal Operand
Instruction Condition Masked Response
Unmasked Response
and Exception Code
ADDPS
ADDPD
ADDSUBPS
ADDSUBPD
HADDPS
HADDPD
SUBPS
SUBPD
HSUBPS
HSUBPD
MULPS
MULPD
DIVPS
DIVPD
SQRTPS
SQRTPD
MAXPS
MAXPD
MINPS
MINPD
CMPPS
CMPPD
ADDSS
ADDSD
SUBSS
SUBSD
MULSS
MULSD
DIVSS
DIVSD
SQRTSS
SQRTSD
MAXSS
MAXSD
MINSS
MINSD
CMPSS
CMPSD
COMISS
COMISD
UCOMISS
UCOMISD
CVTPS2PD
src1 = denormal
1
or
src2 = denormal (and
the DAZ bit in MXCSR
is 0)
res = Result rounded to
the destination precision
and using the bounded
exponent, but only if no
unmasked post-
computation exception
occurs.
src1, src2 unchanged;
#DE = 1
Note that SQRT,
CVTPS2PD, CVTSS2SD,
CVTPD2PS, CVTSD2SS
have only 1 src.