Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 E-17
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
CVTSS2SD
CVTPD2PS
CVTSD2SS
NOTE:
1. For denormal encodings, see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers.”
Table E-16. #O - Numeric Overflow
Instruction Condition Masked Response
Unmasked Response
and Exception Code
ADDPS
ADDSUBPS
HADDPS
SUBPS
HSUBPS
MULPS
DIVPS
ADDSS
SUBSS
MULSS
DIVSS
CVTPD2PS
CVTSD2SS
Rounded result
> largest single
precision finite
normal value
Roundi
ng
Sign
Result & Status
Flags
res = (result calculated
with unbounded
exponent and rounded to
the destination precision)
/ 2
192
#OE = 1
#PE = 1 if the result is
inexact
To
nearest +
-
#OE = 1, #PE = 1
res =
res =
Toward
+
-
#OE = 1, #PE = 1
res = 1.11…1 * 2
127
res =
Toward
+
-
#OE = 1, #PE = 1
res =
res = -1.11…1 * 2
127
Toward
0+
-
#OE = 1, #PE = 1
res = 1.11…1 * 2
127
res = -1.11…1 * 2
127
Table E-15. #D - Denormal Operand
Instruction Condition Masked Response
Unmasked Response
and Exception Code
∞+
∞–
∞–
∞–
∞+ ∞+