Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 E-27
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
// also fix for the SSE and SSE2
// differences in treating two NaN inputs between the
// instructions and other IA-32 instructions
if (isnanf (uiopd1) || isnanf (uiopd2)) {
if (isnanf (uiopd1) && isnanf (uiopd2))
exc_env->result_fval = quietf (uiopd1);
else
exc_env->result_fval = (float)dbl_res24; // exact
if (sw & INVALID_MASK) exc_env->status_flag_invalid_operation = 1;
return (DO_NOT_RAISE_EXCEPTION);
}
// if denormal flag set, and denormal exceptions are enabled, take trap
if (!(exc_env->exc_masks & DENORMAL_MASK) && (sw & DENORMAL_MASK)) {
exc_env->status_flag_denormal_operand = 1;
exc_env->exception_cause = DENORMAL_OPERAND;
return (RAISE_EXCEPTION);
}
// if divide by zero flag set, and divide by zero exceptions are
// enabled, take trap (for divide only)
if (!(exc_env->exc_masks & ZERODIVIDE_MASK) && (sw & ZERODIVIDE_MASK)) {
exc_env->status_flag_divide_by_zero = 1;
exc_env->exception_cause = DIVIDE_BY_ZERO;
return (RAISE_EXCEPTION);
}
// done if the result is a NaN (QNaN Indefinite)
res = (float)dbl_res24;
if (isnanf (*(unsigned int *)&res)) {
exc_env->result_fval = res; // exact
exc_env->status_flag_invalid_operation = 1;
return (DO_NOT_RAISE_EXCEPTION);
}
// dbl_res24 is not a NaN at this point
if (sw & DENORMAL_MASK) exc_env->status_flag_denormal_operand = 1;
// Note: (dbl_res24 == 0.0 && sw & PRECISION_MASK) cannot occur
if (-MIN_SINGLE_NORMAL < dbl_res24 && dbl_res24 < 0.0 ||
0.0 < dbl_res24 && dbl_res24 < MIN_SINGLE_NORMAL) {
result_tiny = 1;
}
// check if the result is huge
if (NEGINFF < dbl_res24 && dbl_res24 < -MAX_SINGLE_NORMAL ||
MAX_SINGLE_NORMAL < dbl_res24 && dbl_res24 < POSINFF) {
result_huge = 1;
}