Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

E-28 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
// at this point, there are no enabled I,D, or Z exceptions
// to take; the instr.
// might lead to an enabled underflow, enabled underflow and inexact,
// enabled overflow, enabled overflow and inexact, enabled inexact, or
// none of these; if there are no U or O enabled exceptions, re-execute
// the instruction using IA-32 double precision format, and the
// user's rounding mode; exceptions must have
// been disabled before calling
// this function; an inexact exception may be reported on the 53-bit
// fsubp, fmulp, or on both the 53-bit and 24-bit conversions, while an
// overflow or underflow (with traps disabled) may be reported on the
// conversion from dbl_res to res
// check whether there is an underflow, overflow,
// or inexact trap to be taken
// if the underflow traps are enabled and the result is
// tiny, take underflow trap
if (!(exc_env->exc_masks & UNDERFLOW_MASK) && result_tiny) {
dbl_res24 = TWO_TO_192 * dbl_res24; // exact
exc_env->status_flag_underflow = 1;
exc_env->exception_cause = UNDERFLOW;
exc_env->result_fval = (float)dbl_res24; // exact
if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1;
return (RAISE_EXCEPTION);
}
// if overflow traps are enabled and the result is huge, take
// overflow trap
if (!(exc_env->exc_masks & OVERFLOW_MASK) && result_huge) {
dbl_res24 = TWO_TO_M192 * dbl_res24; // exact
exc_env->status_flag_overflow = 1;
exc_env->exception_cause = OVERFLOW;
exc_env->result_fval = (float)dbl_res24; // exact
if (sw & PRECISION_MASK) exc_env->status_flag_inexact = 1;
return (RAISE_EXCEPTION);
}
// set control word with rounding mode set to exc_env->rounding_mode,
// double precision, and all exceptions disabled
cw = cw | 0x0200; // set precision to double
__asm {
fldcw WORD PTR cw;
}
switch (exc_env->operation) {
case ADDPS:
case ADDSS:
// perform the addition
__asm {