Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 E-29
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
// load input operands
fld DWORD PTR uiopd1; // may set the denormal status flag
fld DWORD PTR uiopd2; // may set the denormal status flag
faddp st(1), st(0); // rounded to 53 bits, may set the inexact
// status flag
// store result
fstp QWORD PTR dbl_res; // exact, will not set any flag
}
break;
case SUBPS:
case SUBSS:
// perform the subtraction
__asm {
// load input operands
fld DWORD PTR uiopd1; // may set the denormal status flag
fld DWORD PTR uiopd2; // may set the denormal status flag
fsubp st(1), st(0); // rounded to 53 bits, may set the inexact
// status flag
// store result
fstp QWORD PTR dbl_res; // exact, will not set any flag
}
break;
case MULPS:
case MULSS:
// perform the multiplication
__asm {
// load input operands
fld DWORD PTR uiopd1; // may set the denormal status flag
fld DWORD PTR uiopd2; // may set the denormal status flag
fmulp st(1), st(0); // rounded to 53 bits, exact
// store result
fstp QWORD PTR dbl_res; // exact, will not set any flag
}
break;
case DIVPS:
case DIVSS:
// perform the division
__asm {
// load input operands
fld DWORD PTR uiopd1; // may set the denormal status flag
fld DWORD PTR uiopd2; // may set the denormal status flag
fdivp st(1), st(0); // rounded to 53 bits, may set the inexact
// status flag
// store result
fstp QWORD PTR dbl_res; // exact, will not set any flag
}
break;
default: