Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 INDEX-1
INDEX
Numerics
128-bit
packed byte integers data type
, 4-12, 11-5
packed double-precision floating-point
data type
, 4-12, 11-5
packed doubleword integers data type, 4-12
packed quadword integers data type, 4-12
packed SIMD data types, 4-12
packed single-precision floating-point
data type
, 4-12, 10-8
packed word integers data type, 4-12, 11-5
16-bit
address size
, 3-11
operand size, 3-11
286 processor, 2-1
32-bit
address size
, 3-11
operand size, 3-11
64-bit
packed byte integers data type
, 4-11, 9-4
packed doubleword integers data type, 4-11
packed doubleword integers data types, 9-4
packed word integers data type, 4-11, 9-4
64-bit mode
sub-mode of IA-32e
, 3-2
address calculation, 3-12
address size, 3-25
address space, 3-6
BOUND instruction, 7-25
branch behavior, 6-11
byte register limitation, 3-17
CALL instruction, 6-12, 7-24
canonical address, 3-13
CMPS instruction, 7-27
CMPXCHG16B instruction, 7-7
data types, 7-2
DEC instruction, 7-11
decimal arithmetic instructions, 7-14
default operand and address sizes, 3-2
exceptions, 6-19
far pointer, 4-9
feature list, 2-19
GDTR register, 3-6
IDTR register, 3-6
INC instruction, 7-11
instruction pointer, 3-12, 3-24
instructions introduced, 5-31
interrupts, 6-19
introduction, 2-19, 3-2, 7-2
IRET instruction, 7-25
I/O instructions, 7-28
JCC instruction, 6-12, 7-24
JCXZ instruction, 6-12, 7-24
JMP instruction, 6-12, 7-24
LAHF instruction, 7-30
LDTR register, 3-6
legacy modes, 2-20
LODS instruction, 7-27
LOOP instruction, 6-12, 7-24
memory models, 3-11
memory operands, 3-28
MMX technology, 9-2
MOVS instruction, 7-27
MOVSXD instruction, 7-10
near pointer, 4-9
operand addressing, 3-32
operand size, 3-25
operands, 3-28
POPF instruction, 7-30
promoted instructions, 3-2
PUSHA, PUSHAD, POPA, POPAD, 7-9
PUSHF instruction, 7-30
PUSHFD instruction, 7-30
real address mode, 3-11
register operands, 3-28
REP prefix, 7-27
RET instruction, 6-12, 7-24
REX prefix, 3-2, 3-16, 3-25
RFLAGS register, 7-30
RIP register, 3-12
RIP-relative addressing, 3-24, 3-32
SAHF instruction, 7-30
SCAS instruction, 7-27
segment registers, 3-20
segmentation, 3-11, 3-30
SSE extensions, 10-4
SSE2 extensions, 11-4
SSE3 extensions, 12-1
SSSE3 extensions, 12-1
stack behavior, 6-5
STOS instruction, 7-27
TR register, 3-6
x87 FPU, 8-2
See also: IA-32e mode, compatibility mode
8086 processor
, 2-1
8088 processor, 2-1
A
AAA instruction, 7-13
AAD instruction, 7-13
AAM instruction, 7-13
AAS instruction, 7-13
AC (alignment check) flag, EFLAGS register, 3-23
Access rights, segment descriptor, 6-9, 6-14
ADC instruction, 7-11
ADD instruction, 7-11