Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture
INDEX
INDEX-2 Vol. 1
ADDPD instruction
, 11-8
ADDPS instruction, 10-11
Address size attribute
code segment
, 3-24
description of, 3-24
of stack, 6-3
Address sizes, 3-11
Address space
64-bit mode
, 3-2, 3-6
compatibility mode, 3-2
overview of, 3-3
physical, 3-8
Addressing modes
assembler
, 3-32
base, 3-30, 3-31, 3-32
base plus displacement, 3-31
base plus index plus displacement, 3-32
base plus index time scale plus displacement, 3-32
canonical address, 3-13
displacement, 3-30, 3-31, 3-32
effective address, 3-30
immediate operands, 3-26
index, 3-30, 3-32
index times scale plus displacement, 3-32
memory operands, 3-28
register operands, 3-27, 3-28
RIP-relative addressing, 3-24, 3-32
scale factor, 3-30, 3-32
specifying a segment selector, 3-29
specifying an offset, 3-30
specifying offsets in 64-bit mode, 3-32
ADDSD instruction, 11-8
ADDSS instruction, 10-11
ADDSUBPD instruction, 5-26, 12-5
ADDSUBPS instruction, 5-26, 12-5
Advanced media boost, 2-12
advanced smart cache, 2-12
AF (adjust) flag, EFLAGS register, 3-21, A-1
AH register, 3-16
AL register, 3-16
Alignment
words, doublewords, quadwords
, 4-2
AND instruction, 7-14
ANDNPD instruction, 11-10
ANDNPS instruction, 10-13
ANDPD instruction, 11-9
ANDPS instruction, 10-13
Arctangent, x87 FPU operation, 8-29
Arithmetic instructions, x87 FPU, 8-35
Assembler, addressing modes, 3-32
Asymmetric processing model, 12-2
AX register, 3-16
B
B (default size) flag, segment descriptor, 3-24
Base (operand addressing), 3-30, 3-31, 3-32
Basic execution environment, 3-3
Basic programming environment, 7-1, 7-2
B-bit, x87 FPU status word, 8-7
BCD integers
packed
, 4-13
relationship to status flags, 3-22
unpacked, 4-13, 7-13
x87 FPU encoding, 4-13, 4-14
BH register, 3-16
Bias value
numeric overflow
, 8-41
numeric underflow, 8-42
Biased exponent, 4-17
Biasing constant, for floating-point numbers, 4-8
Binary numbers, 1-6
Binary-coded decimal (see BCD)
Bit field
, 4-10
Bit order, 1-4
BL register, 3-16
BOUND instruction, 6-18, 7-25, 7-31
BOUND range exceeded exception (#BR), 6-18
BP register, 3-16
Branch
control transfer instructions
, 7-20
hints, 11-18
on EFLAGS register status flags, 7-22, 8-9
on x87 FPU condition codes, 8-9, 8-28
prediction, 2-8
BSF instruction, 7-19
BSR instruction, 7-19
BSWAP instruction, 7-5
BT instruction, 3-20, 3-22, 7-19
BTC instruction, 3-20, 3-22, 7-19
BTR instruction, 3-20, 3-22, 7-19
BTS instruction, 3-20, 3-22, 7-19
BX register, 3-16
Byte, 4-1
Byte order, 1-4
C
C1 flag, x87 FPU status word, 8-7, 8-37, 8-41, 8-43
C2 flag, x87 FPU status word, 8-7
cache, smart, 2-6
Call gate, 6-9
CALL instruction, 3-24, 6-4, 6-5, 6-9, 7-21, 7-31
Calls (see Procedure calls)
Canonical address
, 3-13
CBW instruction, 7-10
CDQ instruction, 7-10
Celeron processor
description of
, 2-4
CF (carry) flag, EFLAGS register, 3-21, A-1
CH register, 3-16
CL register, 3-16
CLC instruction, 3-22, 7-28
CLD instruction, 3-22, 7-29
CLFLUSH instruction, 11-17
CLI instruction, 13-5