Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture
Vol. 1 INDEX-3
INDEX
CMC instruction, 3-22, 7-28
CMOVcc instructions, 7-4, 7-5
CMP instruction, 7-11
CMPPD instruction, 11-10
CMPPS instruction, 10-13
CMPS instruction, 3-22, 7-26
CMPSD instruction, 11-10
CMPSS instruction, 10-13
CMPXCHG instruction, 7-6
CMPXCHG16B instruction, 7-7
CMPXCHG8B instruction, 7-6
Code segment, 3-19
COMISD instruction, 11-10
COMISS instruction, 10-14
Compare
compare and exchange
, 7-6
integers, 7-11
real numbers, x87 FPU, 8-27
strings, 7-26
Compatibility mode
address space
, 3-2
branch functions, 6-12
call gate descriptors, 6-12
introduction, 2-19, 3-2
memory models, 3-11
MMX technology, 9-2
segmentation, 3-30
SSE extensions, 10-4
SSE2 extensions, 11-4
SSE3 extensions, 12-1
SSSE3 extensions, 12-1
x87 FPU, 8-2
See also: IA-32e mode, 64-bit mode
Compatibility, software
, 1-5
Condition code flags, x87 FPU status word
branching on
, 8-9
conditional moves on, 8-9
description of, 8-6
interpretation of, 8-8
use of, 8-27
Conditional moves, x87 FPU condition codes, 8-9
Constants (floating point), 8-24
Control registers
64-bit mode
, 3-6
overview of, 3-5
Core microarchitecture, 2-12
core microarchitecture, 2-12
Core Solo and Core Duo, 2-6
Cosine, x87 FPU operation, 8-29
CPUID instruction
CLFLUSH flag
, 11-17
CMOVcc feature flag, 7-5
determine support for, 3-23
earlier processors, 14-2
FXSAVE-FXRSTOR flag, 10-21
MMX feature flag, 9-11
processor identification, 14-1
serializing use, 13-7
SSE feature flag, 10-1, 10-9
SSE2 feature flag, 11-1, 12-7, 12-8
SSE3 feature flag, 12-8
SSSE2 feature flag, 12-14
summary of, 7-32
CS register, 3-17, 3-19
CTI instruction, 7-30
Current privilege level (see CPL)
Current stack
, 6-2, 6-4
CVTDQ2PD instruction, 11-14
CVTDQ2PS instruction, 11-14
CVTPD2DQ instruction, 11-14
CVTPD2PI instruction, 11-13
CVTPD2PS instruction, 11-12
CVTPI2PD instruction, 11-13
CVTPI2PS instruction, 10-15
CVTPS2DQ instruction, 11-14
CVTPS2PD instruction, 11-12
CVTPS2PI instruction, 10-16
CVTSD2SI instruction, 11-14
CVTSD2SS instruction, 11-12
CVTSI2SD instruction, 11-14
CVTSI2SS instruction, 10-16
CVTSS2SD instruction, 11-12
CVTSS2SI instruction, 10-16
CVTTPD2DQ instruction, 11-14
CVTTPD2PI instruction, 11-13
CVTTPS2DQ instruction, 11-14
CVTTPS2PI instruction, 10-16
CVTTSD2SI instruction, 11-14
CVTTSS2SI instruction, 10-16
CWD instruction, 7-10
CWDE instruction, 7-10
CX register, 3-16
D
D (default size) flag, segment descriptor, 6-3
DAA instruction, 7-12
DAS instruction, 7-12
Data movement instructions, 7-3
Data pointer, x87 FPU, 8-13
Data registers, x87 FPU, 8-2
Data segment, 3-19
Data types
128-bit packed SIMD
, 4-12
64-bit mode, 7-2
64-bit packed SIMD, 4-11
alignment, 4-2
BCD integers, 4-13, 7-13
bit field, 4-10
byte, 4-1
doubleword, 4-1
floating-point, 4-6
fundamental, 4-1
integers, 4-5
numeric, 4-3
operated on by GP instructions, 7-1, 7-2