Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 2-15

INTEL

64 AND IA-32 ARCHITECTURES

byte, word, or doubleword integers located in MMX registers. These instructions are

useful in applications that operate on integer arrays and streams of integer data that

lend themselves to SIMD processing.

SSE extensions were introduced in the Pentium III processor family. SSE instructions

operate on packed single-precision floating-point values contained in XMM registers

and on packed integers contained in MMX registers. Several SSE instructions provide

state management, cache control, and memory ordering operations. Other SSE

instructions are targeted at applications that operate on arrays of single-precision

floating-point data elements (3-D geometry, 3-D rendering, and video encoding and

decoding applications).

SSE2 extensions were introduced in Pentium 4 and Intel Xeon processors. SSE2

instructions operate on packed double-precision floating-point values contained in

XMM registers and on packed integers contained in MMX and XMM registers. SSE2

integer instructions extend IA-32 SIMD operations by adding new 128-bit SIMD

integer operations and by expanding existing 64-bit SIMD integer operations to

128-bit XMM capability. SSE2 instructions also provide new cache control and

memory ordering operations.

SSE3 extensions were introduced with the Pentium 4 processor supporting Hyper-

Threading Technology (built on 90 nm process technology). SSE3 offers 13 instruc-

tions that accelerate performance of Streaming SIMD Extensions technology,

Streaming SIMD Extensions 2 technology, and x87-FP math capabilities.

SSSE3 extensions were introduced with the Intel Xeon processor 5100 series and

Intel Core 2 processor family. SSSE3 offers 32 instructions to accelerate processing

of SIMD integer data.

Intel 64 architecture allows four generations of 128-bit SIMD extensions to access up

to 16 XMM registers. IA-32 architecture provides 8 XMM registers.