Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

INDEX
INDEX-4 Vol. 1
operated on by MMX technology
, 9-4
operated on by SSE extensions, 10-8
operated on by SSE2 extensions, 11-5
operated on by x87 FPU, 8-18
operated on in 64-bit mode, 4-9
packed bytes, 9-3
packed doublewords, 9-3
packed SIMD, 4-11
packed words, 9-3
pointers, 4-9
quadword, 4-1, 9-3
signed integers, 4-5
strings, 4-10
unsigned integers, 4-5
word, 4-1
DAZ (denormals-are-zeros) flag
MXCSR register
, 10-7
DE (denormal operand exception) flag
MXCSR register
, 11-21
x87 FPU status word, 8-7, 8-39
Debug registers
64-bit mode
, 3-6
legacy modes, 3-5
DEC instruction, 7-11
Decimal integers, x87 FPU, 4-14
Deeper sleep, 2-6
Denormal number (see Denormalized finite number)
Denormal operand exception (#D)
overview of
, 4-27
SSE and SSE2 extensions, 11-21
x87 FPU, 8-38
Denormalization process, 4-20
Denormalized finite number, 4-7, 4-19
Denormals-are-zero
DAZ flag, MXCSR register
, 10-7, 11-3, 11-5,
11-28
mode, 10-7, 11-28
DF (direction) flag, EFLAGS register, 3-22, A-1
DH register, 3-16
DI register, 3-16
Digital media boost, 2-6
Displacement (operand addressing), 3-30, 3-31, 3-32
DIV instruction, 7-12
Divide, 4-28
Divide by zero exception (#Z)
SSE and SSE2 extensions
, 11-22
x87 FPU, 8-40
DIVPD instruction, 11-9
DIVPS instruction, 10-12
DIVSD instruction, 11-9
DIVSS instruction, 10-12
DL register, 3-16
DM (denormal operand exception) mask bit
MXCSR register
, 11-21
x87 FPU, 8-39
x87 FPU control word, 8-11
Double-extended-precision FP format, 4-6
Double-precision floating-point format, 4-6
Doubleword, 4-1
DS register, 3-17, 3-19
Dual-core technology
introduction
, 2-18
DX register, 3-16
Dynamic data flow analysis, 2-8
Dynamic execution, 2-8, 2-12
E
EAX register, 3-14, 3-16
EBP register, 3-14, 3-16, 6-4, 6-8
EBX register, 3-14, 3-16
ECX register, 3-14, 3-16
EDI register, 3-14, 3-16
EDX register, 3-14, 3-16
Effective address, 3-30
EFLAGS register
64-bit mode
, 7-2
condition codes, B-1
cross-reference with instructions, A-1
description of, 3-20
instructions that operate on, 7-28
overview, 3-14
part of basic programming environment, 7-1
restoring from stack, 6-8
saving on a procedure call, 6-8
status flags, 8-9, 8-10, 8-28
use with CMOVcc instructions, 7-4
EIP register
description of
, 3-24
overview, 3-14
part of basic programming environment, 7-1
relationship to CS register, 3-19
EMMS instruction, 9-10, 9-12
Enhanced Intel Deeper Sleep, 2-6
ENTER instruction, 6-19, 6-20, 7-28
ES register, 3-17, 3-19
ES (exception summary) flag
x87 FPU status word
, 8-44
ESC instructions, x87 FPU, 8-22
ESI register, 3-14, 3-16
ESP register, 3-16
ESP register (stack pointer), 3-14, 6-3, 6-4
Exception flags, x87 FPU status word, 8-7
Exception handlers
overview of
, 6-13
SIMD floating-point exceptions, E-1
SSE and SSE2 extensions, 11-25, 11-26
typical actions of a FP exception handler, 4-32
x87 FPU, 8-45
Exception priority, floating-point exceptions, 4-31
Exception-flag masks, x87 FPU control word, 8-11
Exceptions
64-bit mode
, 6-19
description of, 6-13
handler, 6-13
implicit call to handler, 6-1