Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture
Vol. 1 INDEX-5
INDEX
in real-address mode, 6-17
notation, 1-8
vector, 6-13
Exponent, floating-point number, 4-15
F
F2XM1 instruction, 8-31
FABS instruction, 8-25
FADD instruction, 8-25
FADDP instruction, 8-25
Far call
description of
, 6-5
operation, 6-6
Far pointer
16-bit addressing
, 3-11
32-bit addressing, 3-11
64-bit mode, 4-9
description of, 3-8, 4-9
legacy modes, 4-9
Far return operation, 6-6
FBLD instruction, 8-23
FBSTP instruction, 8-23
FCHS instruction, 8-25
FCLEX/FNCLEX instructions, 8-7
FCMOVcc instructions, 8-10, 8-23
FCOM instruction, 8-9, 8-26
FCOMI instruction, 8-10, 8-26
FCOMIP instruction, 8-10, 8-26
FCOMP instruction, 8-9, 8-26
FCOMPP instruction, 8-9, 8-26
FCOS instruction, 8-7, 8-29
FDIV instruction, 8-25
FDIVP instruction, 8-25
FDIVR instruction, 8-25
FDIVRP instruction, 8-25
Feature determination, of processor, 14-1
FIADD instruction, 8-25
FICOM instruction, 8-9, 8-26
FICOMP instruction, 8-9, 8-26
FIDIV instruction, 8-25
FIDIVR instruction, 8-25
FILD instruction, 8-23
FIMUL instruction, 8-25
FINIT/FNINIT instructions, 8-7, 8-11, 8-12, 8-32
FIST instruction, 8-23
FISTP instruction, 8-23
FISTTP instruction, 5-26, 12-4
FISUB instruction, 8-25
FISUBR instruction, 8-25
Flags
cross-reference with instructions
, A-1
Flat memory model, 3-8, 3-18
FLD instruction, 8-23
FLD1 instruction, 8-24
FLDCW instruction, 8-10, 8-32
FLDENV instruction, 8-7, 8-13, 8-15, 8-33
FLDL2E instruction, 8-24
FLDL2T instruction, 8-24
FLDLG2 instruction, 8-24
FLDLN2 instruction, 8-24
FLDPI instruction, 8-24
FLDSW instruction, 8-32
FLDZ instruction, 8-24
Floating-point data types
biasing constant
, 4-8
denormalized finite number, 4-7
description of, 4-6
double extended precision format, 4-6, 4-7
double precision format, 4-6, 4-7
infinites, 4-7
normalized finite number, 4-7
single precision format, 4-6, 4-7
SSE extensions, 10-8
SSE2 extensions, 11-5
storing in memory, 4-9
x87 FPU, 8-18
zeros, 4-7
Floating-point exception handlers
SSE and SSE2 extensions
, 11-25, 11-26
typical actions, 4-32
x87 FPU, 8-45
Floating-point exceptions
denormal operand exception (#D)
, 4-27, 8-39,
11-21, C-1
divide by zero exception (#Z), 4-28, 8-40, 11-22,
C-1
exception conditions, 4-27
exception priority, 4-31
inexact result (precision) exception (#P), 4-30,
8-42, 11-22, C-1
invalid operation exception (#I), 4-27, 8-36, 11-20
invalid-operation exception (#IA), C-1
invalid-operation exception (#IS), C-1
invalid-operation exception (#I), C-1
numeric overflow exception (#O), 4-28, 8-40,
11-22, C-1
numeric underflow exception (#U), 4-29, 8-41,
11-22, C-1
summary of, 4-25, C-1
typical handler actions, 4-32
Floating-point format
biased exponent
, 4-17
description of, 8-18
exponent, 4-15
fraction, 4-15
indefinite, 4-8
QNaN floating-point indefinite, 4-23
real number system, 4-14
sign, 4-15
significand, 4-15
Floating-point numbers
defined
, 4-15
encoding, 4-8