Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

INDEX
INDEX-6 Vol. 1
Flush-to-zero
FZ flag, MXCSR register
, 10-7, 11-3
mode, 10-7
FMUL instruction, 8-25
FMULP instruction, 8-25
FNOP instruction, 8-32
Fopcode compatibility mode, 8-14
FPATAN instruction, 8-29
FPREM instruction, 8-7, 8-25, 8-30
FPREM1 instruction, 8-7, 8-25, 8-30
FPTAN instruction, 8-7
Fraction, floating-point number, 4-15
FRNDINT instruction, 8-25
FRSTOR instruction, 8-7, 8-13, 8-15, 8-33
FS register, 3-17, 3-19
FSAVE/FNSAVE instructions, 8-6, 8-7, 8-13, 8-15,
8-33
FSCALE instruction, 8-31
FSIN instruction, 8-7, 8-29
FSINCOS instruction, 8-7, 8-29
FSQRT instruction, 8-25
FST instruction, 8-23
FSTCW/FNSTCW instructions, 8-10, 8-32
FSTENV/FNSTENV instructions, 8-6, 8-13, 8-15, 8-33
FSTP instruction, 8-23
FSTSW/FNSTSW instructions, 8-6, 8-32
FSUB instruction, 8-25
FSUBP instruction, 8-25
FSUBR instruction, 8-25
FSUBRP instruction, 8-25
FTST instruction, 8-9, 8-27
FUCOM instruction, 8-26
FUCOMI instruction, 8-10, 8-26
FUCOMIP instruction, 8-10, 8-26
FUCOMP instruction, 8-26
FUCOMPP instruction, 8-9, 8-26
FXAM instruction, 8-7, 8-27
FXCH instruction, 8-23
FXRSTOR instruction, 5-13, 8-17, 10-20, 11-34
FXSAVE instruction, 5-13, 8-17, 10-20, 11-34
FXTRACT instruction, 8-25
FYL2X instruction, 8-31
FYL2XP1 instruction, 8-31
G
GDTR register, 3-5, 3-6
General purpose registers
64-bit mode
, 3-6, 3-17
description of, 3-13, 3-14
overview of, 3-3, 3-6
parameter passing, 6-7
part of basic programming environment, 7-1, 7-2
using REX prefix, 3-17
General-purpose instructions
64-bit mode
, 7-2
basic programming environment, 7-1
data types operated on, 7-1, 7-2
description of, 7-1
origin of, 7-1
programming with, 7-1
summary of, 5-2, 7-3
GS register, 3-17, 3-19
H
HADDPD instruction, 5-27, 12-6
HADDPS instruction, 5-26, 12-5
Hexadecimal numbers, 1-6
Horizontal processing model, 12-2
HSUBPD instruction, 5-27, 12-6
HSUBPS instruction, 5-26, 12-6
HT Technology
first processor
, 2-4
implementing, 2-18
introduction, 2-17
I
IA-32 architecture
history of
, 2-1
introduction to, 2-1
IA-32e mode
introduction
, 2-19
segmentation, 3-30
See also: 64-bit mode, compatibility mode
IA32_MISC_ENABLE MSR
, 8-14
ID (identification) flag, EFLAGS register, 3-23
IDIV instruction, 7-12
IDTR register, 3-5, 3-6
IE (invalid operation exception) flag
MXCSR register
, 11-20
x87 FPU status word, 8-7, 8-37, 8-38
IEEE Standard 754, 4-6, 4-14, 8-1
IF (interrupt enable) flag
EFLAGS register
, 3-23, 6-14, 13-5, A-1
IM (invalid operation exception) mask bit
MXCSR register
, 11-20
x87 FPU control word, 8-11
Immediate operands, 3-26
IMUL instruction, 7-12
IN instruction, 5-8, 7-27, 13-4
INC instruction, 7-11
Indefinite
description of
, 4-23
floating-point format, 4-8, 4-18
integer, 4-6, 8-20
packed BCD integer, 4-14
QNaN floating-point, 4-21, 4-23
Index (operand addressing), 3-30, 3-32
Inexact result (precision)
exception (#P), overview
, 4-30
exception (#P), SSE-SSE2 extensions, 11-23
exception (#P), x87 FPU, 8-42
on floating-point operations, 4-24
Infinity control flag, x87 FPU control word, 8-12