Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

INDEX
INDEX-12 Vol. 1
PSUBSW instruction
, 9-8
PSUBUSB instruction, 9-8
PSUBUSW instruction, 9-8
PSUBW instruction, 9-8
PUNPCKHBW instruction, 9-9
PUNPCKHDQ instruction, 9-9
PUNPCKHQDQ instruction, 11-16
PUNPCKHWD instruction, 9-9
PUNPCKLBW instruction, 9-9
PUNPCKLDQ instruction, 9-9
PUNPCKLQDQ instruction, 11-16
PUNPCKLWD instruction, 9-9
PUSH instruction, 6-1, 6-3, 7-7, 7-30
PUSHA instruction, 6-8, 7-7
PUSHF instruction, 3-20, 6-8, 7-29
PUSHFD instruction, 3-20, 6-8, 7-29
PXOR instruction, 9-10
Q
QNaN floating-point indefinite, 4-7, 4-21, 4-23, 8-20
QNaNs
description of
, 4-21
effect on COMISD and UCOMISD, 11-10
encodings, 4-7
operating on, 4-21
rules for generating, 4-22
using in applications, 4-22
Quadword, 4-1, 9-3
Quiet NaN (see QNaN)
R
R8D-R15D registers, 3-16
R8-R15 registers, 3-16
RAX register, 3-16
RBP register, 3-16, 6-5
RBX register, 3-16
RC (rounding control) field
MXCSR register
, 4-24, 10-6
x87 FPU control word, 4-24, 8-12
RCL instruction, 7-18
RCPPS instruction, 10-12
RCPSS instruction, 10-12
RCR instruction, 7-18
RCX register, 3-16
RDI register, 3-16
RDX register, 3-16
Real address mode
handling exceptions in
, 6-17
handling interrupts in, 6-17
memory model, 3-9, 3-10
memory model used, 3-11
not in 64-bit mode, 3-11
overview, 3-1
Real numbers
continuum
, 4-15
encoding, 4-18
notation, 4-17
system, 4-14
Register operands
64-bit mode
, 3-28
legacy modes, 3-27
Register stack, x87 FPU, 8-2
Registers
64-bit mode
, 3-16, 3-20
control registers, 3-5
CR in 64-bit mode, 3-6
debug registers, 3-5
EFLAGS register, 3-14, 3-20
EIP register, 3-14, 3-24
general purpose registers, 3-13, 3-14
instruction pointer, 3-14
machine check registers, 3-5
memory management registers, 3-5
MMX registers, 3-3, 9-3
MSRs, 3-5
MTRRs, 3-5
MXCSR register, 10-6
performance monitoring counters, 3-5
REX prefix, 3-16
segment registers, 3-13, 3-17
x87 FPU registers, 8-1
XMM registers, 3-3, 10-4
Related literature, 1-8
REP/REPE/REPZ/REPNE/REPNZ
prefixes
, 7-26, 13-4
Reserved bits, 1-5
RESET pin, 3-20
RET instruction, 3-24, 6-4, 6-5, 7-21, 7-31
Return instruction pointer, 6-4
Returns, from procedure calls
exception handler, return from
, 6-14
far return, 6-6
inter-privilege level return, 6-10
interrupt handler, return from, 6-14
near return, 6-5
REX prefixes, 3-2, 3-16, 3-25
RF (resume) flag, EFLAGS register, 3-23, A-1
RFLAGS, 3-24
RFLAGS register, 7-30
See EFLAGS register
RIP register
, 6-5
64-bit mode, 7-2
description of, 3-24
relation to EIP, 7-2
ROL instruction, 7-18
ROR instruction, 7-18
Rounding
modes, floating-point operations
, 4-24
modes, x87 FPU, 8-12
toward zero (truncation), 4-25
Rounding control (RC) field
MXCSR register
, 4-24, 10-6
x87 FPU control word, 4-24, 8-12
RSI register, 3-16