Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 INDEX-15
INDEX
handling combinations of masked and unmasked
exceptions
, 11-26
handling masked exceptions, 11-23
handling SIMD floating-point exceptions in
software
, 11-26
handling unmasked exceptions, 11-25, 11-26
inexact result exception (#P), 11-23
initialization of, 11-29
instruction prefixes, effect on SSE and SSE2
instructions
, 11-37
instruction set, 5-21
instructions, 11-6, 12-3, 12-10
interaction of SIMD and x87 FPU floating-point
exceptions
, 11-26
interaction of SSE and SSE2 instructions with x87
FPU and MMX instructions
, 11-31
interfacing with SSE and SSE2 procedures and
functions
, 11-34
intermixing packed and scalar floating-point and
128-bit SIMD integer instructions and data
,
11-32
invalid operation exception (#I), 11-20
logical instructions, 11-9
masked responses to invalid arithmetic
operations
, 11-20
memory ordering instructions, 11-17
MMX technology compatibility, 11-4
numeric overflow exception (#O), 11-22
numeric underflow exception (#U), 11-22
overview of, 11-1
packed 128-Bit SIMD data types, 4-12
packed and scalar floating-point instructions, 11-6
programming environment, 11-3
QNaN floating-point indefinite, 4-23
restoring SSE and SSE2 state, 11-30
REX prefixes, 11-4
saving SSE and SSE2 state, 11-30
saving XMM register state on a procedure or
function call
, 11-34
shuffle instructions, 11-10
SIMD floating-point exception conditions, 11-19
SIMD floating-point exception cross reference,
C-7
SIMD floating-point exception (#XF), 11-25,
11-26
SIMD floating-point exceptions, 11-19
SSE and SSE2 conversion instruction chart, 11-13
SSE compatibility, 11-4
SSE2 feature flag, CPUID instruction, 11-28
unpack instructions, 11-10
updating MMX technology routines using 128-bit
SIMD integer instructions
, 11-35
writing applications with, 11-27
x87 FPU compatibility, 11-4
SSE2 feature flag, CPUID instruction, 11-28, 12-7
SSE2 instructions
descriptions of
, 11-6, 12-3, 12-10
SIMD floating-point exception cross-reference,
C-7
summary of, 5-21
SSE3 extensions
64-bit mode
, 12-1
asymmetric processing, 12-2
compatibility mode, 12-1
DNA exceptions, 12-14
emulation, 12-15
enabling support in a system executive, 12-7
example verifying SS3 support, 12-8, 12-14
exceptions, 12-14
guideline for packed addition/subtraction
instructions
, 12-9
horizontal addition/subtraction instructions, 12-5
horizontal processing, 12-2
instruction that addresses cache line splits, 5-26
instruction that improves X87-FP integer
conversion
, 5-26
instructions for horizontal addition/subtraction,
5-26
instructions for packed addition/subtraction, 5-26
instructions that enhance
LOAD/MOVE/DUPLICATE
, 5-27
instructions that improve synchronization
between agents
, 5-27
LOAD/MOVE/DUPLICATE enhancement
instructions
, 12-4
MMX technology compatibility, 12-2
numeric error flag and IGNNE#, 12-15
packed addition/subtraction instructions, 12-5
programming environment, 12-1
REX prefixes, 12-1
SIMD floating-point exception cross reference,
C-11
specialized 120-bit load instruction, 12-4
SSE compatibility, 12-2
SSE2 compatibility, 12-2
x87 FPU compatibility, 12-2
SSE3 instructions
descriptions of
, 12-3
SIMD floating-point exception
cross-reference
, C-11
summary of, 5-25
SSSE feature flag, CPUID instruction, 12-14
SSSE3 extensions
64-bit mode
, 12-1
asymmetric processing, 12-2
checking for support, 12-14
compatibility, 12-2
compatibility mode, 12-1
data types, 12-1
DNA exceptions, 12-14
emulation, 12-15
enabling support in a system executive, 12-13
exceptions, 12-14
horizontal add/subtract instructions, 12-10
horizontal processing, 12-2