Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

INDEX
INDEX-16 Vol. 1
MMX technology compatibility
, 12-2
multiply and add packed instructions, 12-12
numeric error flag and IGNNE#, 12-15
packed absolute value instructions, 12-11
packed align instruction, 12-13
packed multiply high instructions, 12-12
packed shuffle instruction, 12-12
programming environment, 12-1
SSSE2 compatibility, 12-2
x87 FPU compatibility, 12-2
SSSE3 instructions
descriptions of
, 12-9
summary of, 5-28
Stack
64-bit mode
, 3-6, 6-5
64-bit mode behavior, 6-19
address-size attribute, 6-3
alignment, 6-3
alignment of stack pointer, 6-3
current stack, 6-2, 6-4
description of, 6-1
EIP register (return instruction pointer), 6-4
maximum size, 6-1
number allowed, 6-1
overview of, 3-5
passing parameters on, 6-7
popping values from, 6-1
procedure linking information, 6-4
pushing values on, 6-1
return instruction pointer, 6-4
SS register, 6-1
stack segment, 3-19, 6-1
stack-frame base pointer, EBP register, 6-4
switching
on calls to interrupt and exception handlers
,
6-15
on inter-privilege level calls, 6-11, 6-16
privilege levels, 6-10
width, 6-3
Stack, x87 FPU
stack fault
, 8-9
stack overflow and underflow exception (#IS),
8-7, 8-36, 8-37
Status flags
EFLAGS register
, 3-21, 8-9, 8-10, 8-28
STC instruction, 3-22, 7-28
STD instruction, 3-22, 7-29
STI instruction, 7-30, 13-5
Sticky bits, 8-7
STMXCSR instruction, 10-17, 11-35
STOS instruction, 3-22, 7-26
Streaming SIMD extensions 2 (see SSE2 extensions)
Streaming SIMD extensions (see SSE extensions)
String data type
, 4-10
ST(0), top-of-stack register, 8-4
SUB instruction, 7-11
Superscalar microarchitecture
P6 family microarchitecture
, 2-3
P6 family processors, 2-7
Pentium 4 processor, 2-9
Pentium Pro processor, 2-3
Pentium processor, 2-2
System management mode (see SMM)
T
Tangent, x87 FPU operation, 8-29
Task gate, 6-17
Task register, 3-5
Task state segment (see TSS)
Tasks
exception handler
, 6-17
interrupt handler, 6-17
Temporal data, 10-18
TEST instruction, 7-20
TF (trap) flag, EFLAGS register, 3-23, A-1
Thermal Monitor, 2-6
Tiny number, 4-19
TOP (stack TOP) field
x87 FPU status word
, 8-3, 9-12
TR register, 3-6
Trace cache, 2-10
Transcendental instruction accuracy, 8-31
Trap gate, 6-14
Truncation
description of
, 4-25
with SSE-SSE2 conversion instructions, 4-25
TSS
I/O map base
, 13-5
I/O permission bit map, 13-5
saving state of EFLAGS register, 3-20
U
UCOMISD instruction, 11-10
UCOMISS instruction, 10-14
UD2 instruction, 7-32
UE (numeric underflow exception) flag
MXCSR register
, 11-22
x87 FPU status word, 8-7, 8-42
UM (numeric underflow exception) mask bit
MXCSR register
, 11-22
x87 FPU control word, 8-11, 8-42
Underflow
FPU exception
(see Numeric underflow exception)
numeric, floating-point
, 4-19
x87 FPU stack, 8-36, 8-37
Underflow, x87 FPU stack, 8-37
Unpack instructions
SSE extensions
, 10-14
SSE2 extensions, 11-10
UNPCKHPD instruction, 11-11
UNPCKHPS instruction, 10-14
UNPCKLPD instruction, 11-11
UNPCKLPS instruction, 10-15