Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 2-19
INTEL
®
64 AND IA-32 ARCHITECTURES
ware multi-threading support with both two processor cores and Hyper-Threading
Technology. This means that the Intel Pentium processor Extreme Edition provides
four logical processors in a physical package (two logical processors for each
processor core). The Dual-Core Intel Xeon processor features multi-core, Hyper-
Threading Technology and supports multi-processor platforms.
The Intel Pentium D processor also features multi-core technology. This processor
provides hardware multi-threading support with two processor cores but does not
offer Hyper-Threading Technology. This means that the Intel Pentium D processor
provides two logical processors in a physical package, with each logical processor
owning the complete execution resources of a processor core.
The Intel Core 2 processor family, Intel Xeon processor 5100 series, and Intel Core
Duo processor offer power-efficient multi-core technology. The processor contains
two cores that share a smart second level cache. The Level 2 cache enables efficient
data sharing between two cores to reduce memory traffic to the system bus.
2.2.7 Intel
®
64 Architecture
Intel 64 architecture increases the linear address space for software to 64 bits and
supports physical address space up to 40 bits. The technology also introduces a new
operating mode referred to as IA-32e mode.
IA-32e mode operates in one of two sub-modes: (1) compatibility mode enables a
64-bit operating system to run most legacy 32-bit software unmodified, (2) 64-bit
mode enables a 64-bit operating system to run applications written to access 64-bit
address space.
In the 64-bit mode, applications may access:
• 64-bit flat linear addressing
Figure 2-6. IA-32 Processors that Support Dual-Core
ArchitectualState
System Bus
Execution Engine
Local APIC Local APIC
Execution Engine
Architectual State
Bus Interface
Intel Core Duo Processor
Second Level Cache
Local
APIC
Arch.
State
System Bus
Execution Engine
Local
APIC
Local
APIC
Execution Engine
Arch.
State
Bus Interface Bus Interface
Local
APIC
Arch.
State
Arch.
State
Pentium Processor Extreme Edition
Second Level
Cache
Second Level
Cache
Architectual State
System Bus
Execution Engine
Local APIC Local APIC
Execution Engine
Architectual State
Bus Interface Bus Interface
Pentium D Processor
Second Level
Cache
Second Level
Cache