Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

2-22 Vol. 1
INTEL
®
64 AND IA-32 ARCHITECTURES
Dual-Core Intel
Xeon
Processor 7041
2005 Intel NetBurst
Microarchitecture;
Hyper-Threading
Technology; Intel
64 Architecture;
Dual-core
3
3.00 GHz 321M GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
6.4 GB/s 64 GB 12K µop
Execution
Trace Cache;
16 KB L1;
2MB L2 (4MB
Tot al)
Intel Pentium 4
Processor 672
2005 Intel NetBurst
Microarchitecture;
Hyper-Threading
Technology; Intel
64 Architecture;
Intel Virtualization
Tech no lo gy.
3.80 GHz
164 M GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
6.4 GB/s 64 GB 12K µop
Execution
Trace Cache;
16 KB L1;
2MB L2
Intel Pentium
Processor
Extreme Edition
955
2006 Intel NetBurst
Microarchitecture;
Intel 64
Architecture; Dual
Core;
Intel Virtualization
Tech no lo gy.
3.46 GHz 376M GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
8.5 GB/s 64 GB 12K µop
Execution
Trace Cache;
16 KB L1;
2MB L2
(4MB Total)
Intel Core 2
Extreme
Processor
2006 Intel Core
Microarchitecture;
Dual Core;
Intel 64
Architecture;
Intel Virtualization
Tech no lo gy.
2.93 GHz 291M GP: 32,64
FPU: 80
MMX: 64
XMM: 128
8.5 GB/s 64 GB L1: 64 KB
L2: 4MB (4MB
Tot al)
Intel Xeon
Processor
5160
3
2006 Intel Core
Microarchitecture;
Dual Core;
Intel 64
Architecture;
Intel Virtualization
Tech no lo gy.
3.00 GHz 291M GP: 32, 64
FPU: 80
MMX: 64
XMM: 128
10.6 GB/s 64 GB L1: 64 KB
L2: 4MB (4MB
Tot al)
NOTES:
1. The 64-bit Intel Xeon Processor MP with an 8-MByte L3 supports a multi-processor platform with
a dual system bus; this creates a platform bandwidth with 10.6 GBytes.
2. In Intel Pentium Processor Extreme Edition 840, the size of each on-die cache is listed for each
core. The total size of L2 in the physical package in 2 MBytes.
3. In Dual-Core Intel Xeon Processor 7041, the size of each on-die cache is listed for each core. The
total size of L2 in the physical package in 4 MBytes.
Table 2-2. Key Features of Most Recent Intel 64 Processors (Contd.)
Intel
Processor
Date
Intro-
duced
Micro-
architec-
ture
Top-Bin
Clock
Frequency
at Intro-
duction
Tran-
sistors
Register
Sizes
System
Bus
Band-
width
Max.
Extern.
Addr.
Space
On-Die
Caches