Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 3-3
BASIC EXECUTION ENVIRONMENT
3.2 OVERVIEW OF THE BASIC EXECUTION
ENVIRONMENT
Any program or task running on an IA-32 processor is given a set of resources for
executing instructions and for storing code, data, and state information. These
resources (described briefly in the following paragraphs and shown in Figure 3-1)
make up the basic execution environment for an IA-32 processor.
An Intel 64 processor supports the basic execution environment of an IA-32
processor, and a similar environment under IA-32e mode that can execute 64-bit
programs (64-bit sub-mode) and 32-bit programs (compatibility sub-mode).
The basic execution environment is used jointly by the application programs and the
operating system or executive running on the processor.
• Address space — Any task or program running on an IA-32 processor can
address a linear address space of up to 4 GBytes (2
32
bytes) and a physical
address space of up to 64 GBytes (2
36
bytes). See Section 3.3.6, “Extended
Physical Addressing in Protected Mode,” for more information about addressing
an address space greater than 4 GBytes.
• Basic program execution registers — The eight general-purpose registers,
the six segment registers, the EFLAGS register, and the EIP (instruction pointer)
register comprise a basic execution environment in which to execute a set of
general-purpose instructions. These instructions perform basic integer arithmetic
on byte, word, and doubleword integers, handle program flow control, operate on
bit and byte strings, and address memory. See Section 3.4, “Basic Program
Execution Registers,” for more information about these registers.
• x87 FPU registers — The eight x87 FPU data registers, the x87 FPU control
register, the status register, the x87 FPU instruction pointer register, the x87 FPU
operand (data) pointer register, the x87 FPU tag register, and the x87 FPU opcode
register provide an execution environment for operating on single-precision,
double-precision, and double extended-precision floating-point values, word
integers, doubleword integers, quadword integers, and binary coded decimal
(BCD) values. See Section 8.1, “x87 FPU Execution Environment,” for more
information about these registers.
• MMX registers — The eight MMX registers support execution of single-
instruction, multiple-data (SIMD) operations on 64-bit packed byte, word, and
doubleword integers. See Section 9.2, “The MMX Technology Programming
Environment,” for more information about these registers.
• XMM registers — The eight XMM data registers and the MXCSR register support
execution of SIMD operations on 128-bit packed single-precision and double-
precision floating-point values and on 128-bit packed byte, word, doubleword,
and quadword integers. See Section 10.2, “SSE Programming Environment,” for
more information about these registers.