Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 3-5
BASIC EXECUTION ENVIRONMENT
• Stack — To support procedure or subroutine calls and the passing of parameters
between procedures or subroutines, a stack and stack management resources
are included in the execution environment. The stack (not shown in Figure 3-1) is
located in memory. See Section 6.2, “Stacks,” for more information about stack
structure.
In addition to the resources provided in the basic execution environment, the IA-32
architecture provides the following resources as part of its system-level architecture.
They provide extensive support for operating-system and system-development soft-
ware. Except for the I/O ports, the system resources are described in detail in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A & 3B.
• I/O ports — The IA-32 architecture supports a transfers of data to and from
input/output (I/O) ports. See Chapter 13, “Input/Output,” in this volume.
• Control registers — The five control registers (CR0 through CR4) determine the
operating mode of the processor and the characteristics of the currently
executing task. See Chapter 2, “System Architecture Overview,” in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3A.
• Memory management registers — The GDTR, IDTR, task register, and LDTR
specify the locations of data structures used in protected mode memory
management. See Chapter 2, “System Architecture Overview,” in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3A.
• Debug registers — The debug registers (DR0 through DR7) control and allow
monitoring of the processor’s debugging operations. See Chapter 18, “Debugging
and Performance Monitoring,” in the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 3B.
• Memory type range registers (MTRRs) — The MTRRs are used to assign
memory types to regions of memory. See the sections on MTRRs in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3B.
• Machine specific registers (MSRs) — The processor provides a variety of
machine specific registers that are used to control and report on processor perfor-
mance. Virtually all MSRs handle system related functions and are not accessible
to an application program. One exception to this rule is the time-stamp counter.
The MSRs are described in Appendix B, “Model-Specific Registers (MSRs),” of the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.
• Machine check registers — The machine check registers consist of a set of
control, status, and error-reporting MSRs that are used to detect and report on
hardware (machine) errors. See Chapter 14, “Machine-Check Architecture,” of
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
• Performance monitoring counters — The performance monitoring counters
allow processor performance events to be monitored. See Chapter 18,
“Debugging and Performance Monitoring,” in the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 3B.
The remainder of this chapter describes the organization of memory and the address
space, the basic program execution registers, and addressing modes. Refer to the