Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

3-6 Vol. 1
BASIC EXECUTION ENVIRONMENT
following chapters in this volume for descriptions of the other program execution
resources shown in Figure 3-1:
• x87 FPU registers — See Chapter 8, “Programming with the x87 FPU.”
• MMX Registers — See Chapter 9, “Programming with Intel® MMX™
Technology.”
• XMM registers — See Chapter 10, “Programming with Streaming SIMD
Extensions (SSE),” Chapter 11, “Programming with Streaming SIMD Extensions 2
(SSE2),” and Chapter 12, “Programming with SSE3 and Supplemental SSE3.”
• Stack implementation and procedure calls — See Chapter 6, “Procedure
Calls, Interrupts, and Exceptions.”
3.2.1 64-Bit Mode Execution Environment
The execution environment for 64-bit mode is similar to that described in Section
3.2. The following paragraphs describe the differences that apply.
• Address space — A task or program running in 64-bit mode on an IA-32
processor can address linear address space of up to 2
64
bytes (subject to the
canonical addressing requirement described in Section 3.3.7.1) and physical
address space of up to 2
40
bytes. Software can query CPUID for the physical
address size supported by a processor.
• Basic program execution registers — The number of general-purpose
registers (GPRs) available is 16. GPRs are 64-bits wide and they support
operations on byte, word, doubleword and quadword integers. Accessing byte
registers is done uniformly to the lowest 8 bits. The instruction pointer register
becomes 64 bits. The EFLAGS register is extended to 64 bits wide, and is referred
to as the RFLAGS register. The upper 32 bits of RFLAGS is reserved. The lower 32
bits of RFLAGS is the same as EFLAGS. See Figure 3-2.
• XMM registers — There are 16 XMM data registers for SIMD operations. See
Section 10.2, “SSE Programming Environment,” for more information about
these registers.
• Stack — The stack pointer size is 64 bits. Stack size is not controlled by a bit in
the SS descriptor (as it is in non-64-bit modes) nor can the pointer size be
overridden by an instruction prefix.
• Control registers — Control registers expand to 64 bits. A new control register
(the task priority register: CR8 or TPR) has been added. See Chapter 2, “Intel®
64 and IA-32 Intel® Architectures,” in the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A.
• Debug registers — Debug registers expand to 64 bits. See Chapter 18,
“Debugging and Performance Monitoring,” in the Intel® 64 and IA-32 Architec-
tures Software Developer’s Manual, Volume 3B.
• Descriptor table registers — The global descriptor table register (GDTR) and
interrupt descriptor table register (IDTR) expand to 10 bytes so that they can