Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

3-10 Vol. 1
BASIC EXECUTION ENVIRONMENT
3.3.2 Paging and Virtual Memory
With the flat or the segmented memory model, linear address space is mapped into
the processor’s physical address space either directly or through paging. When using
direct mapping (paging disabled), each linear address has a one-to-one correspon-
dence with a physical address. Linear addresses are sent out on the processor’s
address lines without translation.
When using the IA-32 architecture’s paging mechanism (paging enabled), linear
address space is divided into pages which are mapped to virtual memory. The pages
of virtual memory are then mapped as needed into physical memory. When an oper-
ating system or executive uses paging, the paging mechanism is transparent to an
application program. All that the application sees is linear address space.
In addition, IA-32 architecture’s paging mechanism includes extensions that
support:
• Page Address Extensions (PAE) to address physical address space greater than
4GBytes.
• Page Size Extensions (PSE) to map linear address to physical address in
4-MBytes pages.
See also: Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A.
3.3.3 Memory Organization in 64-Bit Mode
Intel 64 architecture supports physical address space greater than 64 GBytes; the
actual physical address size of IA-32 processors is implementation specific. In 64-bit
mode, there is architectural support for 64-bit linear address space. However,
processors supporting Intel 64 architecture may implement less than 64-bits (see
Section 3.3.7.1). The linear address space is mapped into the processor physical
address space through the PAE paging mechanism.
3.3.4 Modes of Operation vs. Memory Model
When writing code for an IA-32 or Intel 64 processor, a programmer needs to know
the operating mode the processor is going to be in when executing the code and the
memory model being used. The relationship between operating modes and memory
models is as follows:
• Protected mode — When in protected mode, the processor can use any of the
memory models described in this section. (The real-addressing mode memory
model is ordinarily used only when the processor is in the virtual-8086 mode.)
The memory model used depends on the design of the operating system or
executive. When multitasking is implemented, individual tasks can use different
memory models.