Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

3-12 Vol. 1
BASIC EXECUTION ENVIRONMENT
3.3.6 Extended Physical Addressing in Protected Mode
Beginning with P6 family processors, the IA-32 architecture supports addressing of
up to 64 GBytes (2
36
bytes) of physical memory. A program or task could not
address locations in this address space directly. Instead, it addresses individual linear
address spaces of up to 4 GBytes that mapped to 64-GByte physical address space
through a virtual memory management mechanism. Using this mechanism, an oper-
ating system can enable a program to switch 4-GByte linear address spaces within
64-GByte physical address space.
The use of extended physical addressing requires the processor to operate in
protected mode and the operating system to provide a virtual memory management
system. See “36-Bit Physical Addressing Using the PAE Paging Mechanism” in
Chapter 3, “Protected-Mode Memory Management,” of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A.
3.3.7 Address Calculations in 64-Bit Mode
In most cases, 64-bit mode uses flat address space for code, data, and stacks. In
64-bit mode (if there is no address-size override), the size of effective address calcu-
lations is 64 bits. An effective-address calculation uses a 64-bit base and index regis-
ters and sign-extend displacements to 64 bits.
In the flat address space of 64-bit mode, linear addresses are equal to effective
addresses because the base address is zero. In the event that FS or GS segments are
used with a non-zero base, this rule does not hold. In 64-bit mode, the effective
address components are added and the effective address is truncated (See for
example the instruction LEA) before adding the full 64-bit segment base. The base is
never truncated, regardless of addressing mode in 64-bit mode.
The instruction pointer is extended to 64 bits to support 64-bit code offsets. The
64-bit instruction pointer is called the RIP. Table 3-1 shows the relationship between
RIP, EIP, and IP.
Table 3-1. Instruction Pointer Sizes
Generally, displacements and immediates in 64-bit mode are not extended to 64
bits. They are still limited to 32 bits and sign-extended during effective-address
calculations. In 64-bit mode, however, support is provided for 64-bit displacement
and immediate forms of the MOV instruction.
All 16-bit and 32-bit address calculations are zero-extended in IA-32e mode to form
64-bit addresses. Address calculations are first truncated to the effective address
Bits 63:32 Bits 31:16 Bits 15:0
16-bit instruction pointer Not Modified IP
32-bit instruction pointer Zero Extension EIP
64-bit instruction pointer RIP