Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 3-13
BASIC EXECUTION ENVIRONMENT
size of the current mode (64-bit mode or compatibility mode), as overridden by any
address-size prefix. The result is then zero-extended to the full 64-bit address width.
Because of this, 16-bit and 32-bit applications running in compatibility mode can
access only the low 4 GBytes of the 64-bit mode effective addresses. Likewise, a
32-bit address generated in 64-bit mode can access only the low 4 GBytes of the
64-bit mode effective addresses.
3.3.7.1 Canonical Addressing
In 64-bit mode, an address is considered to be in canonical form if address bits 63
through to the most-significant implemented bit by the microarchitecture are set to
either all ones or all zeros.
Intel 64 architecture defines a 64-bit linear address. Implementations can support
less. The first implementation of IA-32 processors with Intel 64 architecture supports
a 48-bit linear address. This means a canonical address must have bits 63 through 48
set to zeros or ones (depending on whether bit 47 is a zero or one).
Although implementations may not use all 64 bits of the linear address, they should
check bits 63 through the most-significant implemented bit to see if the address is in
canonical form. If a linear-memory reference is not in canonical form, the implemen-
tation should generate an exception. In most cases, a general-protection exception
(#GP) is generated. However, in the case of explicit or implied stack references, a
stack fault (#SS) is generated.
Instructions that have implied stack references, by default, use the SS segment
register. These include PUSH/POP-related instructions and instructions using
RSP/RBP as base registers. In these cases, the canonical fault is #SF.
If an instruction uses base registers RSP/RBP and uses a segment override prefix to
specify a non-SS segment, a canonical fault generates a #GP (instead of an #SF). In
64-bit mode, only FS and GS segment-overrides are applicable in this situation.
Other segment override prefixes (CS, DS, ES and SS) are ignored. Note that this also
means that an SS segment-override applied to a “non-stack” register reference is
ignored. Such a sequence still produces a #GP for a canonical fault (and not an #SF).
3.4 BASIC PROGRAM EXECUTION REGISTERS
IA-32 architecture provides 16 basic program execution registers for use in general
system and application programing (see Figure 3-4). These registers can be grouped
as follows:
• General-purpose registers. These eight registers are available for storing
operands and pointers.
• Segment registers. These registers hold up to six segment selectors.