Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

3-20 Vol. 1
BASIC EXECUTION ENVIRONMENT
See Section 3.3, “Memory Organization,” for an overview of how the segment regis-
ters are used in real-address mode.
The four segment registers CS, DS, SS, and ES are the same as the segment regis-
ters found in the Intel 8086 and Intel 286 processors and the FS and GS registers
were introduced into the IA-32 Architecture with the Intel386™ family of processors.
3.4.2.1 Segment Registers in 64-Bit Mode
In 64-bit mode: CS, DS, ES, SS are treated as if each segment base is 0, regardless
of the value of the associated segment descriptor base. This creates a flat address
space for code, data, and stack. FS and GS are exceptions. Both segment registers
may be used as additional base registers in linear address calculations (in the
addressing of local data and certain operating system data structures).
Even though segmentation is generally disabled, segment register loads may cause
the processor to perform segment access assists. During these activities, enabled
processors will still perform most of the legacy checks on loaded values (even if the
checks are not applicable in 64-bit mode). Such checks are needed because a
segment register loaded in 64-bit mode may be used by an application running in
compatibility mode.
Limit checks for CS, DS, ES, SS, FS, and GS are disabled in 64-bit mode.
3.4.3 EFLAGS Register
The 32-bit EFLAGS register contains a group of status flags, a control flag, and a
group of system flags. Figure 3-8 defines the flags within this register. Following
initialization of the processor (either by asserting the RESET pin or the INIT pin), the
state of the EFLAGS register is 00000002H. Bits 1, 3, 5, 15, and 22 through 31 of this
register are reserved. Software should not use or depend on the states of any of
these bits.
Some of the flags in the EFLAGS register can be modified directly, using special-
purpose instructions (described in the following sections). There are no instructions
that allow the whole register to be examined or modified directly.
The following instructions can be used to move groups of flags to and from the proce-
dure stack or the EAX register: LAHF, SAHF, PUSHF, PUSHFD, POPF, and POPFD. After
the contents of the EFLAGS register have been transferred to the procedure stack or
EAX register, the flags can be examined and modified using the processor’s bit
manipulation instructions (BT, BTS, BTR, and BTC).
When suspending a task (using the processor’s multitasking facilities), the processor
automatically saves the state of the EFLAGS register in the task state segment (TSS)
for the task being suspended. When binding itself to a new task, the processor loads
the EFLAGS register with data from the new task’s TSS.
When a call is made to an interrupt or exception handler procedure, the processor
automatically saves the state of the EFLAGS registers on the procedure stack. When