Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 3-21
BASIC EXECUTION ENVIRONMENT
an interrupt or exception is handled with a task switch, the state of the EFLAGS
register is saved in the TSS for the task being suspended.
As the IA-32 Architecture has evolved, flags have been added to the EFLAGS register,
but the function and placement of existing flags have remained the same from one
family of the IA-32 processors to the next. As a result, code that accesses or modifies
these flags for one family of IA-32 processors works as expected when run on later
families of processors.
3.4.3.1 Status Flags
The status flags (bits 0, 2, 4, 6, 7, and 11) of the EFLAGS register indicate the results
of arithmetic instructions, such as the ADD, SUB, MUL, and DIV instructions. The
status flag functions are:
CF (bit 0) Carry flag — Set if an arithmetic operation generates a carry or a
borrow out of the most-significant bit of the result; cleared otherwise.
Figure 3-8. EFLAGS Register
31
29
30 28
27
26 25
24
23
22
21 20 19
18
17
16
0
R
F
I
D
A
C
V
M
X Virtual-8086 Mode (VM)
X Resume Flag (RF)
X Nested Task (NT)
X I/O Privilege Level (IOPL)
S Overflow Flag (OF)
C Direction Flag (DF)
X Interrupt Enable Flag (IF)
X Alignment Check (AC)
XID Flag (ID)
X Virtual Interrupt Pending (VIP)
15
13
14 12
11
10 9
876
543
2
1
0
0
C
F
A
F
P
F
1
D
F
I
F
T
F
S
F
Z
F
N
T
0000
0000000
V
I
P
V
I
F
O
F
I
O
P
L
X Virtual Interrupt Flag (VIF)
X Trap Flag (TF)
S Sign Flag (SF)
S Zero Flag (ZF)
S Auxiliary Carry Flag (AF)
S Parity Flag (PF)
S Carry Flag (CF)
S Indicates a Status Flag
C Indicates a Control Flag
X Indicates a System Flag
Reserved bit positions. DO NOT USE.
Always set to values previously read.