Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

3-24 Vol. 1
BASIC EXECUTION ENVIRONMENT
3.4.3.4 RFLAGS Register in 64-Bit Mode
In 64-bit mode, EFLAGS is extended to 64 bits and called RFLAGS. The upper 32 bits
of RFLAGS register is reserved. The lower 32 bits of RFLAGS is the same as EFLAGS.
3.5 INSTRUCTION POINTER
The instruction pointer (EIP) register contains the offset in the current code segment
for the next instruction to be executed. It is advanced from one instruction boundary
to the next in straight-line code or it is moved ahead or backwards by a number of
instructions when executing JMP, Jcc, CALL, RET, and IRET instructions.
The EIP register cannot be accessed directly by software; it is controlled implicitly by
control-transfer instructions (such as JMP, Jcc, CALL, and RET), interrupts, and
exceptions. The only way to read the EIP register is to execute a CALL instruction and
then read the value of the return instruction pointer from the procedure stack. The
EIP register can be loaded indirectly by modifying the value of a return instruction
pointer on the procedure stack and executing a return instruction (RET or IRET). See
Section 6.2.4.2, “Return Instruction Pointer.”
All IA-32 processors prefetch instructions. Because of instruction prefetching, an
instruction address read from the bus during an instruction load does not match the
value in the EIP register. Even though different processor generations use different
prefetching mechanisms, the function of the EIP register to direct program flow
remains fully compatible with all software written to run on IA-32 processors.
3.5.1 Instruction Pointer in 64-Bit Mode
In 64-bit mode, the RIP register becomes the instruction pointer. This register holds
the 64-bit offset of the next instruction to be executed. 64-bit mode also supports a
technique called RIP-relative addressing. Using this technique, the effective address
is determined by adding a displacement to the RIP of the next instruction.
3.6 OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES
When the processor is executing in protected mode, every code segment has a
default operand-size attribute and address-size attribute. These attributes are
selected with the D (default size) flag in the segment descriptor for the code segment
(see Chapter 3, “Protected-Mode Memory Management,” in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A). When the D flag is set, the
32-bit operand-size and address-size attributes are selected; when the flag is clear,
the 16-bit size attributes are selected. When the processor is executing in real-
address mode, virtual-8086 mode, or SMM, the default operand-size and address-
size attributes are always 16 bits.