Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 3-27

BASIC EXECUTION ENVIRONMENT

example, the following ADD instruction adds an immediate value of 14 to the

contents of the EAX register:

ADD EAX, 14

All arithmetic instructions (except the DIV and IDIV instructions) allow the source

operand to be an immediate value. The maximum value allowed for an immediate

operand varies among instructions, but can never be greater than the maximum

value of an unsigned doubleword integer (2

3.7.2 Register Operands

Source and destination operands can be any of the following registers, depending on

the instruction being executed:

• 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP)

• 16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, or BP)

• 8-bit general-purpose registers (AH, BH, CH, DH, AL, BL, CL, or DL)

• segment registers (CS, DS, SS, ES, FS, and GS)

• EFLAGS register

• x87 FPU registers (ST0 through ST7, status word, control word, tag word, data

operand pointer, and instruction pointer)

• MMX registers (MM0 through MM7)

• XMM registers (XMM0 through XMM7) and the MXCSR register

• control registers (CR0, CR2, CR3, and CR4) and system table pointer registers

(GDTR, LDTR, IDTR, and task register)

• debug registers (DR0, DR1, DR2, DR3, DR6, and DR7)

• MSR registers

Some instructions (such as the DIV and MUL instructions) use quadword operands

contained in a pair of 32-bit registers. Register pairs are represented with a colon

separating them. For example, in the register pair EDX:EAX, EDX contains the high

order bits and EAX contains the low order bits of a quadword operand.

Several instructions (such as the PUSHFD and POPFD instructions) are provided to

load and store the contents of the EFLAGS register or to set or clear individual flags

in this register. Other instructions (such as the Jcc instructions) use the state of the

status flags in the EFLAGS register as condition codes for branching or other decision

making operations.

The processor contains a selection of system registers that are used to control

memory management, interrupt and exception handling, task management,

processor management, and debugging activities. Some of these system registers

are accessible by an application program, the operating system, or the executive

through a set of system instructions. When accessing a system register with a

system instruction, the register is generally an implied operand of the instruction.