Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

3-28 Vol. 1
BASIC EXECUTION ENVIRONMENT
3.7.2.1 Register Operands in 64-Bit Mode
Register operands in 64-bit mode can be any of the following:
• 64-bit general-purpose registers (RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, or
R8-R15)
• 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP, or
R8D-R15D)
• 16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, BP, or R8W-R15W)
• 8-bit general-purpose registers: AL, BL, CL, DL, SIL, DIL, SPL, BPL, and R8L-
R15L are available using REX prefixes; AL, BL, CL, DL, AH, BH, CH, DH are
available without using REX prefixes.
• Segment registers (CS, DS, SS, ES, FS, and GS)
• RFLAGS register
• x87 FPU registers (ST0 through ST7, status word, control word, tag word, data
operand pointer, and instruction pointer)
• MMX registers (MM0 through MM7)
• XMM registers (XMM0 through XMM15) and the MXCSR register
• Control registers (CR0, CR2, CR3, CR4, and CR8) and system table pointer
registers (GDTR, LDTR, IDTR, and task register)
• Debug registers (DR0, DR1, DR2, DR3, DR6, and DR7)
• MSR registers
• RDX:RAX register pair representing a 128-bit operand
3.7.3 Memory Operands
Source and destination operands in memory are referenced by means of a segment
selector and an offset (see Figure 3-9). Segment selectors specify the segment
containing the operand. Offsets specify the linear or effective address of the operand.
Offsets can be 32 bits (represented by the notation m16:32) or 16 bits (represented
by the notation m16:16).
3.7.3.1 Memory Operands in 64-Bit Mode
In 64-bit mode, a memory operand can be referenced by a segment selector and an
offset. The offset can be 16 bits, 32 bits or 64 bits (see Figure 3-10).
Figure 3-9. Memory Operand Address
Offset (or Linear Address)
015
Segment
310
Selector