Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-161
INSTRUCTION SET REFERENCE, A-M
See also:
“Serializing Instructions” in Chapter 7, “Multiple-Processor Management,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A
AP-485, Intel Processor Identification and the CPUID Instruction (Order Number
241618)
Table 3-12. Information Returned by CPUID Instruction
Initial EAX
Value Information Provided about the Processor
Basic CPUID Information
0H EAX
EBX
ECX
EDX
Maximum Input Value for Basic CPUID Information (see Table 3-13)
“Genu”
“ntel”
“ineI”
01H EAX
EBX
ECX
EDX
Version Information: Type, Family, Model, and Stepping ID (see
Figure 3-5)
Bits 7-0: Brand Index
Bits 15-8: CLFLUSH line size (Value ∗ 8 = cache line size in bytes)
Bits 23-16: Maximum number of logical processors in this physical
package.
Bits 31-24: Initial APIC ID
Extended Feature Information (see Figure 3-6 and Table 3-15)
Feature Information (see Figure 3-7 and Table 3-16)
02H EAX
EBX
ECX
EDX
Cache and TLB Information (see Table 3-17)
Cache and TLB Information
Cache and TLB Information
Cache and TLB Information