Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-163
INSTRUCTION SET REFERENCE, A-M
CPUID leaves > 3 < 80000000 are visible only when
IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default).
Deterministic Cache Parameters Leaf
04H
EAX
EBX
ECX
EDX
NOTE:
04H output depends on the initial value in ECX. See also: “INPUT
EAX = 4: Returns Deterministic Cache Parameters for each level on
page 3-180.
Bits 4-0: Cache Type*
Bits 7-5: Cache Level (starts at 1)
Bits 8: Self Initializing cache level (does not need SW initialization)
Bits 9: Fully Associative cache
Bits 13-10: Reserved
Bits 25-14: Maximum number of threads sharing this cache in a
physical package (see note)**
Bits 31-26: Maximum number of processor cores in the physical
package. **, ***
Bits 11-00: L = System Coherency Line Size**
Bits 21-12: P = Physical Line partitions**
Bits 31-22: W = Ways of associativity**
Bits 31-00: S = Number of Sets**
Reserved = 0
NOTES:
* Cache Type fields:
0 = Null - No more caches 3 = Unified Cache
1 = Data Cache 4-31 = Reserved
2 = Instruction Cache
** Add one to the return value to get the result.
*** The returned value is constant for valid initial values in ECX. Valid
ECX values start from 0.
Table 3-12. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value Information Provided about the Processor