Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

3-164 Vol. 2
INSTRUCTION SET REFERENCE, A-M
MONITOR/MWAIT Leaf
5H EAX
EBX
ECX
EDX
Bits 15-00: Smallest monitor-line size in bytes (default is processor's
monitor granularity)
Bits 31-16: Reserved = 0
Bits 15-00: Largest monitor-line size in bytes (default is processor's
monitor granularity)
Bits 31-16: Reserved = 0
Bits 00: Enumeration of Monitor-Mwait extensions (beyond EAX and
EBX registers) supported
Bits 01: Supports treating interrupts as break-event for MWAIT, even
when interrupts disabled
Bits 31 - 02: Reserved
Bits 03 - 00: Number of C0* sub C-states supported using MWait
Bits 07 - 04: Number of C1* sub C-states supported using MWAIT
Bits 11 - 08: Number of C2* sub C-states supported using MWAIT
Bits 15 - 12: Number of C3* sub C-states supported using MWAIT
Bits 19 - 16: Number of C4* sub C-states supported using MWAIT
Bits 31 - 20: Reserved = 0
* The definition of C0 through C4 states for MWAIT extension are
processor-specific C-states, not ACPI C-states.
Thermal and Power Management Leaf
6H EAX
EBX
ECX
EDX
Bits 00: Digital temperature sensor is supported if set
Bits 31 - 01: Reserved
Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor
Bits 31 - 04: Reserved
Bits 00: ACNT/MCNT. The capability to provide a measure of delivered
processor performance (since last reset of the counters), as a
percentage of expected processor performance at frequency specified
in CPUID Brand String
Bits 31 - 01: Reserved = 0
Reserved = 0
Table 3-12. Information Returned by CPUID Instruction (Contd.)
Initial EAX
Value Information Provided about the Processor