Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 1-3
ABOUT THIS MANUAL
generated. The instructions are arranged in alphabetical order. General-purpose, x87
FPU, Intel MMX™ technology, SSE/SSE2/SSE3 extensions, and system instructions
are included.
Chapter 4 — Instruction Set Reference, N-Z. Continues the description of IA-32
instructions started in Chapter 3. It provides the balance of the alphabetized list of
instructions and starts Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 2B.
Chapter 5 — VMX Instruction Reference. Describes the virtual-machine exten-
sions (VMX) of IA-32 instructions. VMX is intended to support virtualization of
processor hardware and a system software layer acting as a host to multiple guest
software environments.
Appendix A — Opcode Map. Gives an opcode map for the IA-32 instruction set.
Appendix B — Instruction Formats and Encodings. Gives the binary encoding of
each form of each IA-32 instruction.
Appendix C — Intel
®
C/C++ Compiler Intrinsics and Functional Equivalents.
Lists the Intel
®
C/C++ compiler intrinsics and their assembly code equivalents for
each of the IA-32 MMX and SSE/SSE2/SSE3 instructions.
1.3 NOTATIONAL CONVENTIONS
This manual uses specific notation for data-structure formats, for symbolic represen-
tation of instructions, and for hexadecimal and binary numbers. A review of this
notation makes the manual easier to read.
1.3.1 Bit and Byte Order
In illustrations of data structures in memory, smaller addresses appear toward the
bottom of the figure; addresses increase toward the top. Bit positions are numbered
from right to left. The numerical value of a set bit is equal to two raised to the power
of the bit position. IA-32 processors are “little endian” machines; this means the
bytes of a word are numbered starting from the least significant byte. Figure 1-1
illustrates these conventions.