Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-173
INSTRUCTION SET REFERENCE, A-M
Figure 3-7. Feature Information Returned in the EDX Register
Table 3-16. More on Feature Information Returned in the EDX Register
Bit # Mnemonic Description
0 FPU Floating Point Unit On-Chip. The processor contains an x87 FPU.
1 VME Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,
including CR4.VME for controlling the feature, CR4.PVI for protected mode
virtual interrupts, software interrupt indirection, expansion of the TSS with
the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.
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