Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-209
INSTRUCTION SET REFERENCE, A-M
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to
Packed Doubleword Integers
Description
Converts four packed single-precision floating-point values in the source operand
(second operand) to four packed signed doubleword integers in the destination
operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register.
When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger than the
maximum signed doubleword integer, the floating-point invalid exception is raised,
and if this exception is masked, the indefinite integer value (80000000H) is returned.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);
DEST[95:64] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64]);
DEST[127:96] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTPS2DQ __m128d _mm_cvtps_epi32(__m128d a)
SIMD Floating-Point Exceptions
Invalid, Precision.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
66 0F 5B
/r
CVTPS2DQ xmm1,
xmm2/m128
Valid Valid Convert four packed single-
precision floating-point values
from xmm2/m128 to four packed
signed doubleword integers in
xmm1.