Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 2-3

INSTRUCTION FORMAT

The LOCK prefix (F0H) forces an operation that ensures exclusive use of shared

memory in a multiprocessor environment. See “LOCK—Assert LOCK# Signal Prefix”

in Chapter 3, “Instruction Set Reference, A-M,” for a description of this prefix.

Repeat prefixes (F2H, F3H) cause an instruction to be repeated for each element of a

string. Use these prefixes only with string instructions (MOVS, CMPS, SCAS, LODS,

STOS, INS, and OUTS). Their use, followed by 0FH, is treated as a mandatory prefix

by a number of SSE/SSE2/SSE3 instructions. Use of repeat prefixes and/or undefined

opcodes with other Intel 64 or IA-32 instructions is reserved; such use may cause

unpredictable behavior.

Branch hint prefixes (2EH, 3EH) allow a program to give a hint to the processor about

the most likely code path for a branch. Use these prefixes only with conditional

branch instructions (Jcc). Other use of branch hint prefixes and/or other undefined

opcodes with Intel 64 or IA-32 instructions is reserved; such use may cause unpre-

dictable behavior.

The operand-size override prefix allows a program to switch between 16- and 32-bit

operand sizes. Either size can be the default; use of the prefix selects the non-default

size. Use of 66H followed by 0FH is treated as a mandatory prefix by some

SSE/SSE2/SSE3 instructions. Other use of the 66H prefix with MMX/SSE/SSE2/SSE3

instructions is reserved; such use may cause unpredictable behavior.

The address-size override prefix (67H) allows programs to switch between 16- and

32-bit addressing. Either size can be the default; the prefix selects the non-default

size. Using this prefix and/or other undefined opcodes when operands for the instruc-

tion do not reside in memory is reserved; such use may cause unpredictable

behavior.

2.1.2 Opcodes

A primary opcode can be 1, 2, or 3 bytes in length. An additional 3-bit opcode field is

sometimes encoded in the ModR/M byte. Smaller fields can be defined within the

primary opcode. Such fields define the direction of operation, size of displacements,

opcode vary depending on the class of operation.

Two-byte opcode formats for general-purpose and SIMD instructions consist of:

• An escape opcode byte 0FH as the primary opcode and a second opcode byte, or

• A mandatory prefix (66H, F2H, or F3H), an escape opcode byte, and a second

opcode byte (same as previous bullet)

For example, CVTDQ2PD consists of the following sequence: F3 0F E6. The first byte

is a mandatory prefix for SSE/SSE2/SSE3 instructions (it is not considered as a

repeat prefix).

Three-byte opcode formats for general-purpose and SIMD instructions consist of:

• An escape opcode byte 0FH as the primary opcode, plus two additional opcode

bytes, or