Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-1
CHAPTER 3
INSTRUCTION SET REFERENCE, A-M
This chapter describes the instruction set for the Intel 64 and IA-32 architectures
(A-M) in IA-32e, protected, Virtual-8086, and real modes of operation. The set
includes general-purpose, x87 FPU, MMX, SSE/SSE2/SSE3/SSSE3, and system
instructions. See also Chapter 4, “Instruction Set Reference, N-Z,” in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 2B.
For each instruction, each operand combination is described. A description of the
instruction and its operand, an operational description, a description of the effect of
the instructions on flags in the EFLAGS register, and a summary of exceptions that
can be generated are also provided.
3.1 INTERPRETING THE INSTRUCTION REFERENCE
PAGES
This section describes the format of information contained in the instruction refer-
ence pages in this chapter. It explains notational conventions and abbreviations used
in these sections.
3.1.1 Instruction Format
The following is an example of the format used for each instruction description in this
chapter. The heading below introduces the example. The table below provides an
example summary table.
CMC—Complement Carry Flag [Example Only]
3.1.1.1 Opcode Column in the Instruction Summary Table
The “Opcode” column in the table above shows the object code produced for each
form of the instruction. When possible, codes are given as hexadecimal bytes in the
Opcode Instruction
64-bit
Mode
Compat/
Leg Mode Description
F5 CMC Valid Valid Complement carry flag.