Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M
3-410 Vol. 2
INSTRUCTION SET REFERENCE, A-M
FPU Flags Affected
C1 Sign of value in ST(0).
C0, C2, C3 See Table 3-47.
Floating-Point Exceptions
None.
Protected Mode Exceptions
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF If there is a pending x87 FPU exception.
Real-Address Mode Exceptions
Same exceptions as in Protected Mode.
Virtual-8086 Mode Exceptions
Same exceptions as in Protected Mode.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
Same exceptions as in Protected Mode.