Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-417
INSTRUCTION SET REFERENCE, A-M
The destination operand contains the first byte of the memory image, and it must be
aligned on a 16-byte boundary. A misaligned destination operand will result in a
general-protection (#GP) exception being generated (or in some cases, an alignment
check exception [#AC]).
The FXSAVE instruction is used when an operating system needs to perform a
context switch or when an exception handler needs to save and examine the current
state of the x87 FPU, MMX technology, and/or XMM and MXCSR registers.
The fields in Table 3-48 are defined in Table 3-49.
XMM7 272
Reserved 288
Reserved 304
Reserved 320
Reserved 336
Reserved 352
Reserved 368
Reserved 384
Reserved 400
Reserved 416
Reserved 432
Reserved 448
Reserved 464
Reserved 480
Reserved 496
Table 3-49. Field Definitions
Field Definition
FCW x87 FPU Control Word (16 bits). See Figure 8-6 in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, for the layout of the
x87 FPU control word.
FSW x87 FPU Status Word (16 bits). See Figure 8-4 in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, for the layout of the
x87 FPU status word.
Table 3-48. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR
Memory Region (Contd.)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0