Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-419
INSTRUCTION SET REFERENCE, A-M
The FXSAVE instruction saves an abridged version of the x87 FPU tag word in the
FTW field (unlike the FSAVE instruction, which saves the complete tag word). The tag
information is saved in physical register order (R0 through R7), rather than in top-of-
stack (TOS) order. With the FXSAVE instruction, however, only a single bit (1 for valid
or 0 for empty) is saved for each tag. For example, assume that the tag word is
currently set as follows:
R7 R6 R5 R4 R3 R2 R1 R0
11 xx xx xx 11 11 11 11
Here, 11B indicates empty stack elements and “xx” indicates valid (00B), zero (01B),
or special (10B).
For this example, the FXSAVE instruction saves only the following 8 bits of informa-
tion:
R7 R6 R5 R4 R3 R2 R1 R0
01110000
Here, a 1 is saved for any valid, zero, or special tag, and a 0 is saved for any empty
tag.
The operation of the FXSAVE instruction differs from that of the FSAVE instruction,
the as follows:
• FXSAVE instruction does not check for pending unmasked floating-point
exceptions. (The FXSAVE operation in this regard is similar to the operation of the
FNSAVE instruction).
• After the FXSAVE instruction has saved the state of the x87 FPU, MMX
technology, XMM, and MXCSR registers, the processor retains the contents of the
registers. Because of this behavior, the FXSAVE instruction cannot be used by an
application program to pass a “clean” x87 FPU state to a procedure, since it
ST0/MM0 through
ST7/MM7
x87 FPU or MMX technology registers. These 80-bit fields contain the x87
FPU data registers or the MMX technology registers, depending on the
state of the processor prior to the execution of the FXSAVE instruction. If
the processor had been executing x87 FPU instruction prior to the FXSAVE
instruction, the x87 FPU data registers are saved; if it had been executing
MMX instructions (or SSE or SSE2 instructions that operated on the MMX
technology registers), the MMX technology registers are saved. When the
MMX technology registers are saved, the high 16 bits of the field are
reserved.
XMM0 through
XMM7
XMM registers (128 bits per field). If the OSFXSR bit in control register CR4
is not set, the FXSAVE instruction may not save these registers. This
behavior is implementation dependent.
Table 3-49. Field Definitions (Contd.)
Field Definition