Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

3-422 Vol. 2
INSTRUCTION SET REFERENCE, A-M
Reserved 448
Reserved 464
Reserved 480
Reserved 496
Table 3-52. Layout of the 64-bit-mode FXSAVE Map with
Default OperandSize
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CS FPU IP FOP FTW FSW FCW 0
MXCSR_MASK MXCSR Reserved DS FPU DP 16
Reserved ST0/MM0 32
Reserved ST1/MM1 48
Reserved ST2/MM2 64
Reserved ST3/MM3 80
Reserved ST4/MM4 96
Reserved ST5/MM5 112
Reserved ST6/MM6 128
Reserved ST7/MM7 144
XMM0 160
XMM1 176
XMM2 192
XMM3 208
XMM4 224
XMM5 240
XMM6 256
XMM7 272
XMM8 288
XMM9 304
XMM10 320
XMM11 336
XMM12 352
XMM13 368
XMM14 384
XMM15
400
Table 3-51. Layout of the 64-bit-mode FXSAVE Map
with Promoted OperandSize (Contd.)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0