Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-469
INSTRUCTION SET REFERENCE, A-M
ELSE (* Generated by INTO *)
THEN #UD;
FI;
IF gate not present
THEN #NP((vector_number ∗ 16) + 2 + EXT); FI;
IF ((vector_number * 16)[IST]
≠ 0)
NewRSP ← TSS[ISTx]; FI;
GOTO TRAP-OR-INTERRUPT-GATE; (* Trap/interrupt gate *)
END;
TASK-GATE: (* PE
= 1, task gate *)
Read segment selector in task gate (IDT descriptor);
IF local/global bit is set to local
or index not within GDT limits
THEN #GP(TSS selector); FI;
Access TSS descriptor in GDT;
IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001)
THEN #GP(TSS selector); FI;
IF TSS not present
THEN #NP(TSS selector); FI;
SWITCH-TASKS (with nesting) to TSS;
IF interrupt caused by fault with error code
THEN
IF stack limit does not allow push of error code
THEN #SS(0); FI;
Push(error code);
FI;
IF EIP not within code segment limit
THEN #GP(0); FI;
END;
TRAP-OR-INTERRUPT-GATE:
Read segment selector for trap or interrupt gate (IDT descriptor);
IF segment selector for code segment is NULL
THEN #GP(0H + EXT); FI; (* NULL selector with EXT flag set *)
IF segment selector is not within its descriptor table limits
THEN #GP(selector + EXT); FI;
Read trap or interrupt handler descriptor;
IF descriptor does not indicate a code segment
or code segment descriptor DPL > CPL
THEN #GP(selector + EXT); FI;
IF trap or interrupt gate segment is not present,
THEN #NP(selector + EXT); FI;
IF code segment is non-conforming and DPL < CPL
THEN