Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-471
INSTRUCTION SET REFERENCE, A-M
NewESP ← TSS[RSP FOR NEW TARGET DPL];
NewSS ← 0;
FI;
FI;
IF segment selector is NULL
THEN #TS(EXT); FI;
IF segment selector index is not within its descriptor table limits
or segment selector's RPL
≠ DPL of code segment,
THEN #TS(SS selector + EXT); FI;
IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)
Read segment descriptor for stack segment in GDT or LDT;
IF stack segment DPL
≠ DPL of code segment,
or stack segment does not indicate writable data segment
THEN #TS(SS selector + EXT); FI;
IF stack segment not present
THEN #SS(SS selector + EXT); FI;
FI
IF 32-bit gate
THEN
IF new stack does not have room for 24 bytes (error code pushed)
or 20 bytes (no error code pushed)
THEN #SS(segment selector + EXT); FI;
FI
ELSE
IF 16-bit gate
THEN
IF new stack does not have room for 12 bytes (error code pushed)
or 10 bytes (no error code pushed);
THEN #SS(segment selector + EXT); FI;
ELSE (* 64-bit gate*)
IF StackAddress is non-canonical
THEN #SS(0);FI;
FI;
FI;
IF (IA32_EFER.LMA = 0) (* Not IA-32e mode *)
THEN
IF instruction pointer is not within code segment limits
THEN #GP(0); FI;
SS:ESP ← TSS(NewSS:NewESP);
(* Segment descriptor information also loaded *)
ELSE
IF instruction pointer points to non-canonical address
THEN #GP(0); FI: