Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

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INSTRUCTION SET REFERENCE, A-M
NT ← 0;
VM ← 0;
RF ← 0;
END;
Flags Affected
The EFLAGS register is pushed onto the stack. The IF, TF, NT, AC, RF, and VM flags
may be cleared, depending on the mode of operation of the processor when the INT
instruction is executed (see the “Operation” section). If the interrupt uses a task
gate, any flags may be set or cleared, controlled by the EFLAGS image in the new
task’s TSS.
Protected Mode Exceptions
#GP(0) If the instruction pointer in the IDT or in the interrupt-, trap-, or
task gate is beyond the code segment limits.
#GP(selector) If the segment selector in the interrupt-, trap-, or task gate is
NULL.
If an interrupt-, trap-, or task gate, code segment, or TSS
segment selector index is outside its descriptor table limits.
If the interrupt vector number is outside the IDT limits.
If an IDT descriptor is not an interrupt-, trap-, or task-descriptor.
If an interrupt is generated by the INT n, INT 3, or INTO instruc-
tion and the DPL of an interrupt-, trap-, or task-descriptor is less
than the CPL.
If the segment selector in an interrupt- or trap-gate does not
point to a segment descriptor for a code segment.
If the segment selector for a TSS has its local/global bit set for
local.
If a TSS segment descriptor specifies that the TSS is busy or not
available.
#SS(0) If pushing the return address, flags, or error code onto the stack
exceeds the bounds of the stack segment and no stack switch
occurs.
#SS(selector) If the SS register is being loaded and the segment pointed to is
marked not present.
If pushing the return address, flags, error code, or stack
segment pointer exceeds the bounds of the new stack segment
when a stack switch occurs.
#NP(selector) If code segment, interrupt-, trap-, or task gate, or TSS is not
present.