Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

3-478 Vol. 2
INSTRUCTION SET REFERENCE, A-M
If pushing the return address, flags, error code, stack segment
pointer, or data segments exceeds the bounds of the stack
segment.
#NP(selector) If code segment, interrupt-, trap-, or task gate, or TSS is not
present.
#TS(selector) If the RPL of the stack segment selector in the TSS is not equal
to the DPL of the code segment being accessed by the interrupt
or trap gate.
If DPL of the stack segment descriptor for the TSS’s stack
segment is not equal to the DPL of the code segment descriptor
for the interrupt or trap gate.
If the stack segment selector in the TSS is NULL.
If the stack segment for the TSS is not a writable data segment.
If segment-selector index for stack segment is outside
descriptor table limits.
#PF(fault-code) If a page fault occurs.
#BP If the INT 3 instruction is executed.
#OF If the INTO instruction is executed and the OF flag is set.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#GP(0) If the instruction pointer in the 64-bit interrupt gate or 64-bit
trap gate is non-canonical.
#GP(selector) If the segment selector in the 64-bit interrupt or trap gate is
NULL.
If the interrupt vector number is outside the IDT limits.
If the interrupt vector number points to a gate which is in non-
canonical space.
If the interrupt vector number points to a descriptor which is not
a 64-bit interrupt gate or 64-bit trap gate.
If the descriptor pointed to by the gate selector is outside the
descriptor table limit.
If the descriptor pointed to by the gate selector is in non-canon-
ical space.
If the descriptor pointed to by the gate selector is not a code
segment.
If the descriptor pointed to by the gate selector doesn’t have the
L-bit set, or has both the L-bit and D-bit set.
If the descriptor pointed to by the gate selector has DPL > CPL.