Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-511
INSTRUCTION SET REFERENCE, A-M
LAHF—Load Status Flags into AH Register
Description
Moves the low byte of the EFLAGS register (which includes status flags SF, ZF, AF, PF,
and CF) to the AH register. Reserved bits 1, 3, and 5 of the EFLAGS register are set in
the AH register as shown in the “Operation” section below.
This instruction executes as described above in compatibility mode and legacy mode.
It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.
Operation
IF 64-Bit Mode
THEN
IF CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1;
THEN AH ← RFLAGS(SF:ZF:0:AF:0:PF:1:CF);
ELSE #UD;
FI;
ELSE
AH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF);
FI;
Flags Affected
None. The state of the flags in the EFLAGS register is not affected.
Protected Mode Exceptions
None.
Real-Address Mode Exceptions
None.
Virtual-8086 Mode Exceptions
None.
Opcode Instruction
64-Bit
Mode
Compat/
Leg Mode Description
9F LAHF Invalid* Valid Load: AH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF).
NOTES:
* Valid in specific steppings. See Description section.