Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-521
INSTRUCTION SET REFERENCE, A-M
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
Real Address Mode Exceptions
GP(0) If any part of the operand would lie outside of the effective
address space from 0 to FFFFH.
For an attempt to set reserved bits in MXCSR.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.
Virtual 8086 Mode Exceptions
Same exceptions as in Real Address Mode.
#PF(fault-code) For a page fault.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#SS(0) If a memory address referencing the SS segment is in a non-
canonical form.
#GP(0) If the memory address is in a non-canonical form.
For an attempt to set reserved bits in MXCSR.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.