Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

3-16 Vol. 2
INSTRUCTION SET REFERENCE, A-M
3.1.1.12 Real-Address Mode Exceptions Section
The “Real-Address Mode Exceptions” section lists the exceptions that can occur when
the instruction is executed in real-address mode (see Table 3-3).
3.1.1.13 Virtual-8086 Mode Exceptions Section
The “Virtual-8086 Mode Exceptions” section lists the exceptions that can occur when
the instruction is executed in virtual-8086 mode (see Table 3-3).
8 #DF—Double Fault Any instruction that can
generate an exception, an
NMI, or an INTR.
Yes Yes Yes
10 #TS—Invalid TSS Task switch or TSS access. Yes Reserved Yes
11 #NP—Segment Not
Present
Loading segment registers or
accessing system segments.
Yes Reserved Yes
12 #SS—Stack
Segment Fault
Stack operations and SS
register loads.
Yes Yes Yes
13 #GP—General
Protection
2
Any memory reference and
other protection checks.
Yes Yes Yes
14 #PF—Page Fault Any memory reference. Yes Reserved Yes
16 #MF—Floating-Point
Error (Math Fault)
Floating-point or WAIT/FWAIT
instruction.
Yes Yes Yes
17 #AC—Alignment
Check
Any data reference in
memory.
Yes Reserved Yes
18 #MC—Machine
Check
Model dependent machine
check errors.
Yes Yes Yes
19 #XM—SIMD
Floating-Point
Numeric Error
SSE/SSE2/SSE3 floating-point
instructions.
Yes Yes Yes
NOTES:
1. Apply to protected mode, compatibility mode, and 64-bit mode.
2. In the real-address mode, vector 13 is the segment overrun exception.
Table 3-3. Intel 64 and IA-32 General Exceptions (Contd.)
Vector
No. Name Source
Protected
Mode
1
Real
Address
Mode
Virtual
8086
Mode