Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-553
INSTRUCTION SET REFERENCE, A-M
Virtual-8086 Mode Exceptions
#UD The LAR instruction cannot be executed in virtual-8086 mode.
Compatibility Mode Exceptions
Same exceptions as in Protected Mode.
64-Bit Mode Exceptions
#SS(0) If the memory operand effective address referencing the SS
segment is in a non-canonical form.
#GP(0) If the memory operand effective address is in a non-canonical
form.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and the memory operand effec-
tive address is unaligned while the current privilege level is 3.