Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

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INSTRUCTION SET REFERENCE, A-M
At the opcode level, the reg field within the ModR/M byte specifies which of the
control registers is loaded or read. The 2 bits in the mod field are always 11B. The
r/m field specifies the general-purpose register loaded or read.
These instructions have the following side effect:
• When writing to control register CR3, all non-global TLB entries are flushed (see
“Translation Lookaside Buffers (TLBs)” in Chapter 3 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 3A).
The following side effects are implementation specific for the Pentium 4, Intel Xeon,
and P6 processor family. Software should not depend on this functionality in all Intel
64 or IA-32 processors:
• When modifying any of the paging flags in the control registers (PE and PG in
register CR0 and PGE, PSE, and PAE in register CR4), all TLB entries are flushed,
including global entries.
• If the PG flag is set to 1 and control register CR4 is written to set the PAE flag to
1 (to enable the physical address extension mode), the pointers in the page-
directory pointers table (PDPT) are loaded into the processor (into internal, non-
architectural registers).
• If the PAE flag is set to 1 and the PG flag set to 1, writing to control register CR3
will cause the PDPTRs to be reloaded into the processor. If the PAE flag is set to 1
and control register CR0 is written to set the PG flag, the PDPTRs are reloaded
into the processor.
In 64-bit mode, the instruction’s default operation size is 64 bits. Use of the REX.R
prefix permits access to additional registers (R8-R15). Use of the REX.W or 66H
prefix is ignored. See the summary chart at the beginning of this section for encoding
data and limits.
See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 21 of
the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, for
more information about the behavior of this instruction in VMX non-root operation.
Operation
DEST ← SRC;
Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are undefined.
Protected Mode Exceptions
#GP(0) If the current privilege level is not 0.
If an attempt is made to write invalid bit combinations in CR0
(such as setting the PG flag to 1 when the PE flag is set to 0, or
setting the CD flag to 0 when the NW flag is set to 1).