Intel 64 and IA-32 Architectures Software Developers Manual Volume 2A, Instruction Set Reference, A-M

Vol. 2 3-599
INSTRUCTION SET REFERENCE, A-M
If an attempt is made to write a 1 to any reserved bit in CR4.
If any of the reserved bits are set in the page-directory pointers
table (PDPT) and the loading of a control register causes the
PDPT to be loaded into the processor.
Real-Address Mode Exceptions
#GP If an attempt is made to write a 1 to any reserved bit in CR4.
If an attempt is made to write invalid bit combinations in CR0
(such as setting the PG flag to 1 when the PE flag is set to 0).
Virtual-8086 Mode Exceptions
#GP(0) These instructions cannot be executed in virtual-8086 mode.
Compatibility Mode Exceptions
#GP(0) If the current privilege level is not 0.
If an attempt is made to write invalid bit combinations in CR0
(such as setting the PG flag to 1 when the PE flag is set to 0, or
setting the CD flag to 0 when the NW flag is set to 1).
If an attempt is made to write a 1 to any reserved bit in CR3.
If an attempt is made to leave IA-32e mode by clearing
CR4.PAE[bit 5].
64-Bit Mode Exceptions
#GP(0) If the current privilege level is not 0.
If an attempt is made to write invalid bit combinations in CR0
(such as setting the PG flag to 1 when the PE flag is set to 0, or
setting the CD flag to 0 when the NW flag is set to 1).
Attempting to clear CR0.PG[bit 32].
If an attempt is made to write a 1 to any reserved bit in CR4.
If an attempt is made to write a 1 to any reserved bit in CR8.
If an attempt is made to write a 1 to any reserved bit in CR3.
If an attempt is made to leave IA-32e mode by clearing
CR4.PAE[bit 5].